Raised source/drain junctions can provide shallow junctions with low series resistance. However, previously proposed processes for forming raised source/drain junctions have required either 1) selective epitaxy or 2) enhanced etching of polycrystalline Si compared to single crystal Si. Selective epitaxy is difficult to control, and suffers from spurious growth (on isolation), incomplete growth (on contaminated regions), and faceting. Achieving highly selective etching of polysilicon to single crystal Si is also difficult to achieve. Hence, a process for forming raised source/drain junctions is required which is more readily implemented in commercially feasible manufacturing processes.
U.S. Pat. No. 5,682,055 discloses a process for forming a polycide gate stack, and in particular discloses in FIG. 6A an embodiment for forming raised source/drain regions in which a polysilicon layer 44 is conformally deposited over the transistor gate, exposed substrate and the field oxide regions. It is preferably doped after it is deposited to a desired doping level to allow for separate doping of n- and p-type regions. Because of its conformality, in order to fill the opening 17 to form the raised source/drain regions, the polysilicon layer 44 is deposited to a thickness wherein the lowermost portion 46 of the polysilicon layer 44 is above the upper surface 22 of the field oxide regions 12 and preferably above the upper surface of the capping layer 30. A planar sacrificial layer 48, for example spin-on-glass or photoresist having an etch rate of 1:1 with the polysilicon layer 44 may be formed over the polysilicon layer 44.
Referring to FIG. 6B, an etch of the sacrificial layer 48 and the polysilicon layer 44 is performed to expose an upper surface of the field oxide regions 12 forming the raised source/drain regions 50 in opening 17. The etch chemistry is selective to the polysilicon so that the underlying layers are not etched. The etch may be a wet etch, dry etch, CMP or combination of these three, which are selective to the sacrificial layer 48 and the polysilicon layer 44, etching the sacrificial layer and the polysilicon layer at the same rate, but which does not substantially etch the sidewall spacers 34, the capping layer 30 or the silicide layer 28, if the capping layer is not formed, and the field oxide regions 12, including any etch stop layer formed.
The polysilicon raised source/drain regions 50 may also be silicided for both the transistor gate and the epitaxial raised source/drain regions. The silicide regions 52 of the polysilicon raised source/drain regions 50 also lowers the resistivity of the raised source/drain regions, while the raised source/drain regions 50 prevent an undesired amount of the substrate silicon from being consumed, again reducing the possibility of junction leakage and punch-through. The sidewall spacers 34 and capping layer 30 electrically isolate the raised source/drain regions 50 from the gate electrode 18 of the transistor.
The process described in U.S. Pat. No. 5,682,055 has several disadvantages. For example, the use of reactive ion etching to pattern the polysilicon for the raised source/drain contacts makes recess depth control difficult leading to inconsistent process results and inconsistent device performance.
Further, the process of U.S. Pat. No. 5,682,055 requires the use of a gate cap insulator. The requirement of a gate cap insulator makes it more difficult to fabricate dual work function devices (i.e., p+ and n+ gates on the same wafer) which are required for CMOS logic. More specifically, the use of a gate cap insulator means that the gates must be doped relatively early in the process (i.e., before the gate cap insulator is deposited). This often results in boron penetration of the gate oxide during subsequent anneals (sidewall oxidation, junction anneals), leading to poor control of the threshold voltage of the pFETs.
Hence, there is a desire for improved fabrication processes and designs which overcome the problems associate with processes and designs of U.S. Pat. No. 5,682,055.